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Research Contents

Research Contents

PROJECTS > Research Contents

1-2 Ultra-low power electronics convergence devices

Participants
Topic 1 : development of SERS platform for various detection applications based on nanotransfer printing
Participants
  • Yeon Sik Jung, KAIST (Materials Scinece and Engineering)
Purpose
  • Formation of ultra-sensitive chemical, bio-sensor substrate on arbitrary substrates using nano-transfer printing method
Research Contents
  • Fabrication and evaluation of large area SERS substrate through nanotransfer printing
    - Replication of 8 inch wafer scale template for high throughput SERS substrate
  • development of cost-effective and high-throughput SERS platform

Expected Contribution
  • Early diagnosis of disease, Detection and analysis of toxic factor
  • Application of portable sensor

Topic 2 : The development of an innovative ultra-low power electronic device
Participants
  • Yang-Kyu Choi, KAIST (Electrical Engineering)
Purpose
  • The development of an innovative ultra-low power electronic device.
연구내용
  • It is necessary to make new devices that have high on-current and very low off-current in low operating voltage. A vertically integrated multiple channel-based field-effect transistor (FET) with the highest number of nanowires is developed on a bulk silicon substrate without use of wet etching. The advantage of GAA device using nanowire is that it can solve problems related with short channel effect and power consumption problem. However, in the case of SOI wafer, the producing cost can be high. Moreover, the driving current is increased by 5-fold due to the inherent vertically stacked five-level nanowires, thus showing good feasibility of three-dimensional integration-based high performance transistor. The developed fabrication process, which is simple and reproducible, is used to create multiple stiction-free and uniformly sized nanowires with the aid of the one-route all-dry etching process (ORADEP). Furthermore, the proposed FET is revamped to create nonvolatile memory with the adoption of a charge trapping layer for enhanced practicality. Thus, this research suggests an ultimate design for the end-of-the-roadmap devices to overcome the limits of scaling.

Expected Contribution
  • The proposed electronic devices can be used in a memory and logic that demand on high reliability and ultra-low power consumption. Elaborately, the demonstration of such a device is meaningful in view of the suppression of the short-channel effects induced static power consumption, the enhancement of the performance, and the effective scalability. Furthermore, an application to NVM using the device was successfully introduced with the achievement of stable memory functions such as a large memory window, a robust retention time, and reliable witching endurance. The findings here are expected to be effective with regard to the development of highly integrated 3-D NVM created by means of a fully CMOS compatible process. Thus, this research suggests an optimum configuration for end-of-the-roadmap devices aimed at versatile future electronics. Ultimately, through these technologies, great economical effect and improved qualities of products can be expected.
Topic 3 : Low power, high speed chip-to-chip interface using dielectric waveguide
Participants
  • Hyeon-Min Bae, KAIST (Electrical Engineering)
Purpose
  • For decades, copper based interconnect has been widely adopted for various high-speed wireline communications owing to its cost/power efficiencies. However, the skin effect, caused by electromagnetic induction, exerts a fundamental limitation on the utilization of metallic interconnects for high-speed communications. As such, it is generally believed that optical interconnection will eventually substitute the entire metallic interconnects in the coming future as the data rate increases. However, the wide spread use of optical interconnects is severely challenged by overwhelming power increase over metallic interconnects and their unrealistic replacement cost. Given that, we are proposing a completely new ultra high speed/cost-effective/low power/short reach (1~2m) interconnect solution.
Research Contents
  • A low-power, high-speed chip-to-chip interface platform using dielectric waveguide.
    - Find out the optimized the structure and the dimension of dielectric waveguide and the type of dielectric material and realize it.
    - Design microstrip circuits to maximize the power transfer to dielectric waveguide.
    - Design mm-Wave high frequency package model.
    - Design low-power CMOS 60GHz transceiver.
    - Newly developed solution will meet challenging key specifications including:
      a) Cost of <10¢/pin can be achieved via low cost material and manufacturing processes
      b) Energy of <10pJ/bit can be achieved since power-hungry RX equalizer is not necessary
      c) Data rate of <25Gb/s through process scaling
      d) High density through no E/O and O/E conversion

Expected Contribution
  • A solely realizable cost-efficient and low-power solution for 100GE chip-to-chip interface and next generation of 400GE market.
  • A number of target applications: Data center, Memory link, Thunderbolt/USB, etc.
TOPIC 4 : Integration of micro-endoscopic module in conventional endoscopic systems
Participants
  • Ki-Hun Jeong, KAIST (Bio & Brain Engineering)
Purpose
  • Integration of fiber scanning based OCT micro-endoscopic module in conventional endoscopic systems
Research Contents
  • Optimization of micro-endoscopic module for packaging
  • Silicon structure fabrication for low voltage operation

Expected Contribution
  • The novel endoscopic system invented from this project will be directly utilized in high resolution endoscopy for the clinical applications and it will provide new direction for early diagnosis as well as excellent initiative transferring MEMS technology to new biomedical instrumentation.
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