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In-Cheol Park

2-1-1 Project Director

Project : Multi-core Platform for Smart IT Systems
Purpose The objective is to develop key technologies required to design and implement an ultra-low-power scalable multicore platform. To achieve this, we will study a core architecture that guarantees scalability and availability of multi/many-cores, focusing on smart sensor network systems. In addition, automatic synthesis methodology will be developed to enable fast prototyping and provide user-friendly environment.
Contents Multi-core platforms based on 32-bit RISC processors will be developed to provide reliable computing performance for multi-dimensional smart IT systems. Starting from the development of energy-efficient computing architecture, we will focus on how to build a multi-core platform and how to scale it to deliver a performance tailored to a specific application. For this, diverse platforms ranging from dual-core, quad-core, and octal-core systems will be developed one by one.

In multi/many-core systems, power management and load balancing are significant to achieve low-power consumption and sustain high performance. As the computing power is lost in context switching, ahardware-based thread manager may be effective in ensuring the balanced workload and increasing the throughput of the entire system. In addition, a special architecture consisting of a master processor and a slave processor will be investigated to boost the performance without much increasing the hardware complexity and to guarantee power efficiency in idle time.

Furthermore, the system synthesis will be automated by developing systematic methods to Integrate and interconnect many IPs into the multi-core platform mentioned above. To ensure a user-friendly system, this study will include the development of automatic Interface layer synthesis, device driver synthesis, and essential supporting peripherals, such as cache controller, MMU, and on-chip bus.
Expected Contribution Through this research, we can have concrete knowledge on the multi-core computing architecture which is scalable in terms of energy and performance. In addition, this work will achieve a systematic methodology to build smart IT systems as well as well-defined processor systems. The low-power, low-complexity multi-core system is valuable in itself, and it plays an important role in ensuring a leading position in the market of smart sensor systems.
Publication
No Title Year Phase
5 Partially Parallel Encoder Architecture for Long Polar Codes 2015.03. Phase 2
2nd year
4 Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems 2015.03. Phase 2
2nd year
3 Tail-Overlapped SISO Decoding for High-Throughput LTE-Advanced Turbo Decoders 2014.09. Phase 2
2nd year
2 Single-step glitch-free NAND-based digitally controlled delay lines using dual loops 2014.06 Phase 2
1st year
1 Immediate Exchange of Extrinsic Information for High-Throughput Turbo Decoding 2012.12 Phase 1
2nd year
1
Patent
No Title Country Date Phase
4 메모리 관리 유닛, 이를 포함하는 멀티 코어 프로세서, 컴퓨터 시스템 및 데이터 관리 방법 KR 2014-01-22 Phase 2
1st year
3 일관성 관리 방법, 일관성 관리 회로, 이를 포함하는 캐시 장치 및 반도체 장치 KR 2012-06-27 Phase 1
1st year
2 메모리 관리 유닛, 이를 포함하는 멀티 코어 프로세서, 컴퓨터 시스템 및 데이터 관리 방법 KR 2012-06-27 Phase 1
1st year
1 가상 보드 플랫폼, 시스템-온-칩 시뮬레이션 장치, 시스템-온-칩 시뮬레이션 방법 및 시스템-온-칩 검증 방법 KR 2012-06-27 Phase 1
1st year
1
Conference
No title Conference Name Date Phase
5 단일 포트 메모리를 이용한 고성능 저면적 HEVC Deblocking 필터 제안 대한전자공학회 계학술대회 2014-06-25 Phase 2
1st year
4 저면적, 고성능의 HEVC 적응적 루프 필터 설계 대한전자공학회 계학술대회 2014-06-25 Phase 2
1st year
3 Adaptive Metric Calculation for Improving Detection Capability of MIMO Detectors 2013 IEEE 77th Vehicular Technology Conference 2013-06-02 Phase 1
2nd year
2 Memory-optimized Hybrid Decoding Method for Multirate Turbo Codes 2013 IEEE 77th Vehicular Technology Conference 2013-06-02 Phase 1
2nd year
1 QEMU를 활용한 at91sam9xe(ARM926EJ-S) processor simulator 구현 대한전자공학회 하계학술대회 2012-06-27 Phase 1
1st year
1
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