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Byung-Gook Park

1-1-2 Project Director

Project : Ultralow-power nano device and reconfigurable 3-D integrated system
Purpose In order to minimize the energy loss of an electronic system at system level as well as device level, we secure the core technologies to construct neuromorphic electronic systems. To attain this goal, we develop a unit synaptic device, re-configurable synapse array and neuron circuit. Furthermore, we also develop interconnect technology essential for 2- and 3-D array formation. For highly-reliable and ultra-low-power characteristics, we develop electrical models and scaling-down technology.
Contents The fabrication and electrical modeling of synaptic devices and array : Based on the understanding on neuron/synapse system, a unique synaptic device and reconfigurable synapse array are constructed. In order to apply them to neuromorphic system, we also secure the electrical model.

The design/implementation of neuron circuits and system configuration: Considering power consumption and reliable characteristics, we design and manufacture the neuron circuits. As we constitute a neuromorphic system with neurons and synapse array, the system can be utilized to new information processing system that may replace conventional CPU.

3-D interconnect technology: To imitate the behavior of neural system and increase the integration density, we develop optical interconnects with low power and high efficiency. By expanding the array architecture in 3-D using the interconnect, a high-density 3-D neuromorphic system is pursued. At the same time, fully Si-based inter-layer interconnection technology is developed.
Expected Contribution To strengthen the national competitiveness in 3-D reconfigurable IT system area by securing the related core intellectual properties.
To secure path-breaking technologies and outstanding workforce on ultra-low-power system, device and, and manufacturing process and related material sciences.
To create an innovative new technology by technology convergence overcoming current technology limitations.
To secure corporate competitiveness and create new jobs.
Publication
No Title Year Phase
25 Resistive switching characteristics of silicon nitride-based RRAM depending on top electrode metals 2015.07. Phase 2
2nd year
24 Neuron Circuit Using a Thyristor and Inter-neuron Connection with Synaptic Devices 2015.06. Phase 2
2nd year
23 Integrate-and-Fire Neuron Circuit and Synaptic Device with Floating Body MOSFETs 2014.12. Phase 2
2nd year
22 Reduction of Current Crowding in InGaN-based Blue Light-Emitting Diodes by Modifying Metal Contact Geometry 2014.10. Phase 2
2nd year
21 Analysis of trap and its impact on InGaN-based blue light-emitting diodes using current-transient methodology 2014.05 Phase 2
1st year
20 Improved Internal Quantum Efficiency of GaN-based Light Emitting Diodes using p-AlGaN Trench in Multi-Quantum Well 2014.05 Phase 2
1st year
19 Analysis of conduction mechanism in silicon nitride-based RRAM 2014.03. Phase 2
1st year
18 Investigation of bipolar resistive switching characteristics in Si3N4-based RRAM with metal-insulator-silicon structure 2014.03. Phase 2
1st year
17 Vertical stack array of one-time programmable nonvolatile memory based on pn-junction diode and its operation scheme for faster access 2014.02. Phase 2
1st year
16 Effects of germanium incorporation on optical performances of silicon germanium passive devices for group-IV photonic integrated circuits 2014.02. Phase 2
1st year
1 2 3
Patent
No Title Country Date Phase
23 SILICON-COMPATIBLE GERMANIUM-BASED TRANSISTOR WITH HIGH-HOLE-MOBILITY US 2014-12-01 Phase 2
2nd year
22 SILICON-COMPATIBLE COMPOUND JUNCTIONLESS FIELD EFFECT TRANSISTOR US 2014-11-04 Phase 2
2nd year
21 Germanium Electroluminescence Device and Fabrication Method of the Same US 2014-10-30 Phase 2
2nd year
20 나노 팁 구조를 갖는 저항성 메모리 소자 및 이를 이용한 메모리 어레이와 그 제조방법 KR 2014-10-14 Phase 2
2nd year
19 플로팅 바디 소자를 이용한 뉴런 발화동작 모방 반도체 회로 Korea 2014-03-05 Phase 2
1st year
18 실리콘 집적가능한 게르마늄 기반의 높은 정공 이동도를 갖는 트랜지스터 KR 2013-11-29 Phase 2
1st year
17 스페이서 구조를 갖는 저항성 메모리 소자 및 그 제조방법 KR 2013-09-05 Phase 2
1st year
16 SYNAPTIC SEMICONDUCTOR DEVICE AND OPERATION METHOD THEREOF USA 2013-09-05 Phase 2
1st year
15 독립된 듀얼 게이트의 핀펫 구조를 갖는 터널링 전계효과 트랜지스터 및 그 제조방법 KR 2013-07-10 Phase 1
2nd year
14 METHODS OF FABRICATING SEMICONDUCTOR DEVICE USING HIGH-K LAYER FOR SPACER ETCH STOP AND RELATED DEVICES USA 2013-07-09 Phase 1
2nd year
1 2 3
Conference
No title Conference Name Date Phase
62 Advanced Materials and Devices for Electronics and Photonic Convergence Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD) 2014-07-01 Phase 2
1st year
61 Resistive Switching Characteristics of Silicon Nitride-based RRAM depending on the Top Electrode Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD) 2014-07-01 Phase 2
1st year
60 O2-Enhanced Surface Treatment of Ge Epitaxially Grown on Si for Heterogeneous Ge Technology IEEE International Symposium on Consumer Electronic (ISCE) 2014-06-22 Phase 2
1st year
59 Optimization and Modeling of npn-type Selector for Resistive RRAM in Cross-point Array Structure Silicon Nanoelectronics Workshop 2014-06-08 Phase 2
1st year
58 Switching and Conduction Mechanism of Cu/Si3N4/Si RRAM with Si CMOS Compatibility Silicon Nanoelectronics Workshop 2014-06-08 Phase 2
1st year
57 Integrate and Fire neuron circuit and synaptic device with Floating body MOSFETs Silicon Nanoelectronics Workshop 2014-06-08 Phase 2
1st year
56 SiGeSn ternary system for next-generation electronic and photonic devices Korean Conference on Semiconductors (KCS) 2014-02-24 Phase 2
1st year
55 Integrate-and-Fire neuron circuit and synaptic device with floating body MOSFETs Korean Conference on Semiconductors (KCS) 2014-02-24 Phase 2
1st year
54 Current crowding improvement of InGaN-based blue light-emitting diodes by modifying metal contact geometry Korean Conference on Semiconductors (KCS) 2014-02-24 Phase 2
1st year
53 Low-standby power and high-performance InAs/InGaAs/InP heterojunction tunneling field-effect transistor International Conference on Electronics, Information and Communication 2014-01-30 Phase 2
1st year
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