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Hyeon-Min Bae

1-2-5 Project Director

Project : Low power, high speed chip-to-chip interface using dielectric waveguide
Purpose · To develop a low-power, high-speed chip-to-chip interface platform using dielectric waveguide.
· To resolve the issues of established technology; skin loss of metal interconnect and cost-inefficiency of optical interconnect.
· To develop wideband, low-loss, cost-efficient dielectric waveguide and low-power CMOS 60GHz transceiver.
Contents · A low-power, high-speed chip-to-chip interface platform using dielectric waveguide.
- Find out the optimized the structure and the dimension of dielectric waveguide and the type of dielectric material and realize it.
- Design microstrip circuits to maximize the power transfer to dielectric waveguide.
- Design mm-Wave high frequency package model.
- Design low-power CMOS 60GHz transceiver.
Expected Contribution · A solely realizable cost-efficient and low-power solution for 100GE chip-to-chip interface and next generation of 400GE market.
· A number of target applications: Data center, Memory link, Thunderbolt/USB, etc.
Publication
No Title Year Phase
1 Variable-Precision distributed arithmetic (VPDA) MIMO equalizer for power-and-area-efficient 112Gbps optical DP-QPSK systems 2013.01 Phase 1
2nd year
1
Patent
No Title Country Date Phase
6 저전력, 고속 멀티-채널 유전체 웨이브가이드를 이용한 칩-대-칩 인터페이스 KR 2014-03-12 Phase 2
1st year
5 LOW POWER, HIGH SPEED MULTI-CHANNEL CHIP-TO_CHIP INTERFACE USING DIELECTRIC WAVEGUIDE USA 2013-12-11 Phase 2
1st year
4 LOW POWER, HIGH SPEED MULTI-CHANNEL CHIP-TO_CHIP INTERFACE USING DIELECTRIC WAVEGUIDE PCT 2013-09-12 Phase 2
1st year
3 VARIABLE-PRECISION DISTRIBUTED ARITHMETIC MULTI-INPUT MULTI-OUTPUT EQUALIZER FOR POWER-AND-AREA-EFFICIENT OPTICAL DUAL-POLARIZATION QUADRATURE PHASE-SHIFT-KEYING SYSTEM US 2013-01-11 Phase 1
2nd year
2 도파관을 이용한 멀티채널 칩대칩 저전력 고속 유선 인터페이스 KR 2012-12-27 Phase 1
2nd year
1 Variable Precision QPSK Equalizer for the Reduction of Computation power US 2012-03-29 Phase 1
1st year
1
Conference
No title Conference Name Date Phase
 
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