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Yang-Kyu Choi

1-2-3 Project Director

Project : The development of an innovative ultra-low power electronic device
Purpose It has been currently difficult to downsize the device scale because of high power consumption and thermal problems caused by integration of electronic circuits and memories. The purpose of this research is to make new devices that have high performance by solving power consumption problems. Through the method that makes high performance and reduces power consumption, using the existing CMOS process technology, nano devices such as an innovative electronic devices. Finally, these devices will be used in ultra low power system and electronic circuits as a memory and logic.
Contents It is necessary to make new devices that have high on-current and very low off-current in low operating voltage. A vertically integrated multiple channel-based field-effect transistor (FET) with the highest number of nanowires is developed on a bulk silicon substrate without use of wet etching. The advantage of GAA device using nanowire is that it can solve problems related with short channel effect and power consumption problem. However, in the case of SOI wafer, the producing cost can be high. Moreover, the driving current is increased by 5-fold due to the inherent vertically stacked five-level nanowires, thus showing good feasibility of three-dimensional integration-based high performance transistor. The developed fabrication process, which is simple and reproducible, is used to create multiple stiction-free and uniformly sized nanowires with the aid of the one-route all-dry etching process (ORADEP). Furthermore, the proposed FET is revamped to create nonvolatile memory with the adoption of a charge trapping layer for enhanced practicality. Thus, this research suggests an ultimate design for the end-of-the-roadmap devices to overcome the limits of scaling.
Expected Contribution The proposed electronic devices can be used in a memory and logic that demand on high reliability and ultra-low power consumption. Elaborately, the demonstration of such a device is meaningful in view of the suppression of the short-channel effects induced static power consumption, the enhancement of the performance, and the effective scalability. Furthermore, an application to NVM using the device was successfully introduced with the achievement of stable memory functions such as a large memory window, a robust retention time, and reliable witching endurance. The findings here are expected to be effective with regard to the development of highly integrated 3-D NVM created by means of a fully CMOS compatible process. Thus, this research suggests an optimum configuration for end-of-the-roadmap devices aimed at versatile future electronics. Ultimately, through these technologies, great economical effect and improved qualities of products can be expected.
Publication
No Title Year Phase
35 A Core Compact Model for Multiple-Gate Junctionless FETs 2015.07. Phase 2
2nd year
34 Direct Observation of Carbon Filament in Water-Resistant Organic memory 2015.06. Phase 2
2nd year
33 Vertically stacked thin triboelectric nanogenerator for wind energy harvesting 2015.05. Phase 2
2nd year
32 High-performance nanopattern triboelectric generatorbyblockcopolymerlithography 2015.03. Phase 2
2nd year
31 Self-cleaning hybrid energy harvester to generate power from raindrop and sunlight 2015.03. Phase 2
2nd year
30 A Novel FinFET With High-Speed and Prolonged Retention for Dynamic Memory 2014.12. Phase 2
2nd year
29 Accurate extraction of mobility in carbon nanotube network transistors using C-V and IV 2014.11. Phase 2
2nd year
28 Nature-Replicated Nano-in-Micro Structures for Triboelectric Energy Harvesting 2014.10. Phase 2
2nd year
27 A mechanical and electrical transistor structure(METS) with a sub-2 nm naanogap for effective voltage scaling 2014.07 Phase 2
1st year
26 Multiplex electrical detection of avian influenza and human immunodeficiency virus with an underlap-embedded silicon nanowire field-effect transistor 2014.05. Phase 2
1st year
1 2 3 4
Patent
No Title Country Date Phase
18 접촉 대전 발전기 및 그 제조 방법 KR 2014-12-02 Phase 2
2nd year
17 접촉 대전 발전기 및 그 제조 방법 KR 2014-10-14 Phase 2
2nd year
16 전계 효과 트랜지스터의 제조 방법 KR 2014-10-13 Phase 2
2nd year
15 코팅 대전층을 포함하는 접촉 대전 발전기 및 그 생성 방법 KR 2014-09-23 Phase 2
2nd year
14 전자 소자 및 그 제조방법 KR 2014-09-19 Phase 2
2nd year
13 롤형상을 이용한 슬라이딩 접촉 대전 발전기 및 그 제조 방법 KR 2014-09-02 Phase 2
2nd year
12 스위치 소자 및 그 제조방법 KR 2013-12-06 Phase 2
1st year
11 전계효과 트랜지스터를 이용한 바이오센서 KR 2013-10-14 Phase 2
1st year
10 전계효과 트랜지스터를 이용한 바이오센서 KR 2013-10-14 Phase 2
1st year
9 전계효과 트랜지스터 및 그 제조방법 KR 2013-09-17 Phase 2
1st year
1 2
Conference
No title Conference Name Date Phase
3 A Novel SiNW/CMOS Hybrid Biosensor for High Sensitivity/Low Noise IEEE International Electron Device Meeting 2013-12-09 Phase 2
1st year
2 An Independent Bias Scheme for the Improved Electrical Detection of Label-free DNA Using an Electrostatic Micromechanical Biosensor KMEMS 2013-04-04 Phase 1
2nd year
1 Highly Endurable Floating Body Cell Memory: Vertical Biristor IEEE International Electron Device Meeting 2012-12-10 Phase 1
2nd year
1
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