컨텐츠 바로가기 영역
주메뉴로 바로가기
본문으로 바로가기
A better IT world for all,
Center for Integrated Smart Sensors is making it with creative SMART IT convergences system technologies, we can make a better
where everyone's dreams come true.
About CISS Research Team

Research Team

Organization Board Auditor Director Research Team Administrative Team Technology Commercialization Team Evaluation Committee

2-1-1 Project Director

이미지
In-Cheol Park

Project : Multi-core Platform for Smart IT Systems

  • Purpose

    The objective is to develop key technologies required to design and implement an ultra-low-power scalable multicore platform. To achieve this, we will study a core architecture that guarantees scalability and availability of multi/many-cores, focusing on smart sensor network systems. In addition, automatic synthesis methodology will be developed to enable fast prototyping and provide user-friendly environment.

  • Contents

    Multi-core platforms based on 32-bit RISC processors will be developed to provide reliable computing performance for multi-dimensional smart IT systems. Starting from the development of energy-efficient computing architecture, we will focus on how to build a multi-core platform and how to scale it to deliver a performance tailored to a specific application. For this, diverse platforms ranging from dual-core, quad-core, and octal-core systems will be developed one by one. In multi/many-core systems, power management and load balancing are significant to achieve low-power consumption and sustain high performance. As the computing power is lost in context switching, ahardware-based thread manager may be effective in ensuring the balanced workload and increasing the throughput of the entire system. In addition, a special architecture consisting of a master processor and a slave processor will be investigated to boost the performance without much increasing the hardware complexity and to guarantee power efficiency in idle time. Furthermore, the system synthesis will be automated by developing systematic methods to Integrate and interconnect many IPs into the multi-core platform mentioned above. To ensure a user-friendly system, this study will include the development of automatic Interface layer synthesis, device driver synthesis, and essential supporting peripherals, such as cache controller, MMU, and on-chip bus.

  • Expected Contribution

    Through this research, we can have concrete knowledge on the multi-core computing architecture which is scalable in terms of energy and performance. In addition, this work will achieve a systematic methodology to build smart IT systems as well as well-defined processor systems. The low-power, low-complexity multi-core system is valuable in itself, and it plays an important role in ensuring a leading position in the market of smart sensor systems.

List